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StdLogicVector
0.1
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An implementation of the std_logic_vector VHDL data type in C++. More...
#include <iostream>#include <sstream>#include <string>#include <gmp.h>#include <gmpxx.h>#include <math.h>#include <algorithm>#include "StdLogicVector.h"Functions | |
| ostream & | operator<< (ostream &_os, const StdLogicVector &_stdLogicVec) |
| Provide a nice stream output showing the value of the StdLogicVector in hexadecimal representation and also its length. | |
An implementation of the std_logic_vector VHDL data type in C++.
In order to generate bit-true C++ models of VHDL implementations, this file provides an equivalent C++ class of the std_logic_vector data type available in VHDL. Since the value of a StdLogicVector can be of arbitrary length, its actual value is internally represented using the GMP library [1] for arbitrary arithmetic functions. Therefore, this class represents kind of a wrapper around the GMP library, which allows simple arithmetic as it is often used when designing with VHDL or other hardware description languages.