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AES-128
1.0
Fully Unrolled VHDL Implementation of AES-128
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AES-128
1.0
Fully Unrolled VHDL Implementation of AES-128
|
AES-128 package. More...
Package Body >> aes128PkgFunctions | |
| Word | conv_word ( input: in std_logic_vector (31 downto 0) ) |
| Matrix | shift_rows ( input: in Matrix ) |
| Matrix | "xor" ( left: in Matrix , right: in std_logic_vector ) |
Libraries | |
| ieee | |
Use Clauses | |
| ieee.std_logic_1164.all | |
Constants | |
| ZERO_BYTE | Byte := ( others = > ' 0 ' ) |
| ZERO_WORD | Word := ( others = >ZERO_BYTE ) |
| ZERO_MATRIX | Matrix := ( others = >ZERO_WORD ) |
Types | |
| Word | array ( 0 to 3 ) of Byte |
| Matrix | array ( 0 to 3 ) of Word |
| roundkeyArrayType | array ( 0 to 10 ) of std_logic_vector ( 127 downto 0 ) |
Subtypes | |
| Byte | std_logic_vector ( 7 downto 0 ) |
AES-128 package.
A package for the 128-bit version of the Advanced Encryption Standard (AES) design. A couple of types, constants, and functions are defined herein, which are used throughout the whole design.
1.8.6 
