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AES-128
1.0
Fully Unrolled VHDL Implementation of AES-128
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| AES-128 package | |
| High-throughput implementation of AES-128 | |
| Behavioral architecture of AES-128 | |
| AES-128 single cipher round | |
| Behavioral architecture description of a single AES round | |
| AES-128 key expansion | |
| Behavioral architecture description of AES-128 key expansion | |
| AES MixColumn operation (single column) | |
| Behavioral architecture of the "MixColumn" function | |
| AES state MixColumn | |
| Structural architecture of the "MixMatrix" function | |
| AES S-box | |
| Behavioral architecture of the Canright AES S-box | |
| AES S-box implementation based on a look-up table | |
| AES substitute matrix function | |
| Structural architecture of the "SubMatrix" function | |
| AES substitude word function (SubWord) | |
| Structural architecture of the "SubWord" function |