AES-128  1.0
Fully Unrolled VHDL Implementation of AES-128
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cipherRound.vhd File Reference

AES-128 single cipher round. More...

Entities

cipherRound  entity
 AES-128 single cipher round. More...
 
Behavioral  architecture
 Behavioral architecture description of a single AES round. More...
 

Detailed Description

AES-128 single cipher round.

Project:
VLSI Book - AES-128 Example
Author
Michael Muehlberghuber (mbgh@.nosp@m.iis..nosp@m.ee.et.nosp@m.hz.c.nosp@m.h)
Company:
Integrated Systems Laboratory, ETH Zurich
Copyright
Copyright (C) 2014 Integrated Systems Laboratory, ETH Zurich
Date
2014-06-05
Last Updated:
2014-06-05
Platform:
Simulation: ModelSim; Synthesis: Synopsys, Xilinx XST/Vivado
Standard:
VHDL'93/02