AES-128
1.0
Fully Unrolled VHDL Implementation of AES-128
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Behavioral architecture description of a single AES round. More...
Components | |
subMatrix | <Entity subMatrix> |
mixMatrix | <Entity mixMatrix> |
Signals | |
SubMatrixOut_D | Matrix |
ShiftRowsOut_D | Matrix |
MixMatrixOut_D | Matrix |
Instantiations | |
submatrix_1 | subMatrix <Entity subMatrix> |
mixmatrix_1 | mixMatrix <Entity mixMatrix> |
Behavioral architecture description of a single AES round.