AES-128  1.0
Fully Unrolled VHDL Implementation of AES-128
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cipherRound Entity Reference

AES-128 single cipher round. More...

Inheritance diagram for cipherRound:
subMatrix mixMatrix subWord mixColumn sbox aes128

Entities

Behavioral  architecture
 Behavioral architecture description of a single AES round. More...
 

Libraries

ieee 
work 

Use Clauses

ieee.std_logic_1164.all 
work.aes128Pkg.all 

Ports

StateIn_DI   in Matrix
 The internal state of AES being applied to this round.
Roundkey_DI   in std_logic_vector ( 127 downto 0 )
 The roundkey to be used for the current AES round.
StateOut_DO   out Matrix
 The resulting state of AES after applying this round.

Detailed Description

AES-128 single cipher round.

Implements a single cipher round of the AES-128 encryption algorithm, which can then be instantiated multiple times in order to create a high-throughput architecture.


The documentation for this class was generated from the following file: