AES-128  1.0
Fully Unrolled VHDL Implementation of AES-128
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keyExpansion Entity Reference

AES-128 key expansion. More...

Inheritance diagram for keyExpansion:
subWord sbox aes128

Entities

Behavioral  architecture
 Behavioral architecture description of AES-128 key expansion. More...
 

Libraries

ieee 
work 

Use Clauses

ieee.std_logic_1164.all 
ieee.numeric_std.all 
work.aes128Pkg.all 

Ports

Clk_CI   in std_logic
 System clock.
Reset_RBI   in std_logic
 Asynchronous, active-high reset.
Start_SI   in std_logic
 Determines whether a new cipherkey has been applied or not.
Cipherkey_DI   in std_logic_vector ( 127 downto 0 )
 The cipher key (master key) for the encryption/decryption.
Roundkeys_DO   out roundkeyArrayType
 The generated round keys.

Detailed Description

AES-128 key expansion.

The present design implements the key expansion for the 128-bit version of the Advanced Encryption Standard (AES). Since the design targets a high-throughput implementation, the key expansion is implemented using pipeline register between each roundkey calculation.

Member Data Documentation

Start_SI in std_logic
Port

Determines whether a new cipherkey has been applied or not.

0...No new cipherkey has been applied.
1...New cipherkey has been applied.

The documentation for this class was generated from the following file: