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AES-128
1.0
Fully Unrolled VHDL Implementation of AES-128
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Behavioral architecture description of AES-128 key expansion. More...
Functions | |
| Word | "xor" ( left: in Word , right: in Word ) |
| std_logic_vector | conv_std_logic_vector ( input: in Word ) |
| std_logic_vector | conv_std_logic_vector ( column0: in Word column1: in Word column2: in Word column3: in Word ) |
Processes | |
| pComb_CalcAllRndKeysDisabled | ( EnRndKeys_SP ) |
| pSequ_FlipFlops | ( Clk_CI , Reset_RBI ) |
Components | |
| subWord | <Entity subWord> |
Constants | |
| RCON | byteArrayType := ( x " 01 " , x " 02 " , x " 04 " , x " 08 " , x " 10 " , x " 20 " , x " 40 " , x " 80 " , x " 1B " , x " 36 " ) |
Types | |
| byteArrayType | array ( 0 to 9 ) of std_logic_vector ( 7 downto 0 ) |
| subWordArrayType | array ( 0 to 9 ) of Word |
| expkeyArrayType | array ( 0 to 43 ) of Word |
| rconArrayType | array ( 0 to 9 ) of Word |
Signals | |
| ExpKey_DN | expkeyArrayType |
| ExpKey_DP | expkeyArrayType |
| SubWordIn_D | subWordArrayType |
| SubWordOut_D | subWordArrayType |
| Rcon_D | rconArrayType |
| Roundkeys_D | roundkeyArrayType |
| EnRndKeys_SN | std_logic_vector ( 0 to 9 ) |
| EnRndKeys_SP | std_logic_vector ( 0 to 9 ) |
| AllRndKeysDisabled_S | std_logic |
Instantiations | |
| subwords | subWord <Entity subWord> |
Behavioral architecture description of AES-128 key expansion.