The present design implements the cipher of the 128-bit version of the Advanced Encryption Standard (AES). Since the design targets a high-throughput implementation, both the key expansion and the actual cipher are pipeline.
Inputs and outputs are registered. While the plaintext and the ciphertext are registered in the top entity, the cipherkey is registered within the key expansion entity. Due to the input buffering, the actual encryption starts with a delay of one clock cycle. After that, both the key expansion and the encryption are executed “in parallel”.
General Information
File | aes128.vhd |
Title | High-throughput implementation of AES-128 |
Project | VLSI Book AES-128 Example |
Author | Michael Muehlberghuber (mb.nosp@m.gh@iis.ee..nosp@m.ethz.ch) |
Company | Integrated Systems Laboratory, ETH Zurich |
Copyright | Copyright © 2014 Integrated Systems Laboratory, ETH Zurich |
File Created | 2014-10-16 |
Last Updated | 2014-10-16 |
Platform | Simulation=QuestaSim; Synthesis=Synopsys |
Standard | SystemVerilog 1800-2009 |
Revision Control System Information
File ID | $Id: aes128.sv 23 2014-10-20 09:23:20Z u59323933 $ |
Revision | $Revision: 23 $ |
Local Date | $Date: 2014-10-20 11:23:20 +0200 (Mon, 20 Oct 2014) $ |
Modified By | $Author: u59323933 $ |
Major Revisions
2014-10-16 (v1.0) | Created (mbgh) |
Summary
aes128 | The present design implements the cipher of the 128-bit version of the Advanced Encryption Standard (AES). |
Types | |
stateArrayType | An array holding 10 Matrices. |
Methods | |
to_matrix | Converts a logic[127:0] to a Matrix. |
to_logic | Converts a matrix to a logic[127:0]. |