mixColumn

The present design implements the MixColumn operation of the Advanced Encryption Standard (AES).

General Information

FilemixColumn.vhd
TitleAES MixColumn operation (single column)
ProjectVLSI Book AES-128 Example
AuthorMichael Muehlberghuber (mb.nosp@m.gh@iis.ee..nosp@m.ethz.ch)
CompanyIntegrated Systems Laboratory, ETH Zurich
CopyrightCopyright © 2014 Integrated Systems Laboratory, ETH Zurich
File Created2014-10-16
Last Updated2014-10-16
PlatformSimulation=QuestaSim; Synthesis=Synopsys
StandardSystemVerilog 1800-2009

Revision Control System Information

File ID$Id: mixColumn.sv 23 2014-10-20 09:23:20Z u59323933 $
Revision$Revision: 23 $
Local Date$Date: 2014-10-20 11:23:20 +0200 (Mon, 20 Oct 2014) $
Modified By$Author: u59323933 $

Major Revisions

2014-10-16 (v1.0)Created (mbgh)
Summary
mixColumnThe present design implements the MixColumn operation of the Advanced Encryption Standard (AES).
Ports
In_DI32 bit input to the MixColumn function.
Out_DO32 bit output from the MixColumn function.

Ports

In_DI

32 bit input to the MixColumn function.

Out_DO

32 bit output from the MixColumn function.

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