Implements a single cipher round of the AES-128 encryption algorithm, which can then be instantiated multiple times in order to create a high-throughput architecture.
File | cipherRound.vhd |
Title | AES-128 single cipher round |
Project | VLSI Book AES-128 Example |
Author | Michael Muehlberghuber (mb@iis.ee. ethz.ch) gh |
Company | Integrated Systems Laboratory, ETH Zurich |
Copyright | Copyright © 2014 Integrated Systems Laboratory, ETH Zurich |
File Created | 2014-10-16 |
Last Updated | 2014-10-16 |
Platform | Simulation=QuestaSim; Synthesis=Synopsys |
Standard | SystemVerilog 1800-2009 |
File ID | $Id: cipherRound.sv 23 2014-10-20 09:23:20Z u59323933 $ |
Revision | $Revision: 23 $ |
Local Date | $Date: 2014-10-20 11:23:20 +0200 (Mon, 20 Oct 2014) $ |
Modified By | $Author: u59323933 $ |
2014-10-16 (v1.0) | Created (mbgh) |
cipherRound | Implements a single cipher round of the AES-128 encryption algorithm, which can then be instantiated multiple times in order to create a high-throughput architecture. |
Ports | |
StateIn_DI | The matrix to be fed into the cipher round. |
Roundkey_DI | The roundkey to be used for the cipher round. |
StateOut_DO | The output from the cipher round. |