The present design implements the key expansion for the 128-bit version of the Advanced Encryption Standard (AES). Since the design targets a high-throughput implementation, the key expansion is implemented using pipeline register between each roundkey calculation.
| File | keyExpansion.vhd |
| Title | AES-128 key expansion |
| Project | VLSI Book AES-128 Example |
| Author | Michael Muehlberghuber (mbgh@iis.ee.ethz.ch) |
| Company | Integrated Systems Laboratory, ETH Zurich |
| Copyright | Copyright © 2014 Integrated Systems Laboratory, ETH Zurich |
| File Created | 2014-10-16 |
| Last Updated | 2014-10-16 |
| Platform | Simulation=QuestaSim; Synthesis=Synopsys |
| Standard | SystemVerilog 1800-2009 |
| File ID | $Id: keyExpansion.sv 42 2014-10-30 12:17:09Z u59323933 $ |
| Revision | $Revision: 42 $ |
| Local Date | $Date: 2014-10-30 13:17:09 +0100 (Thu, 30 Oct 2014) $ |
| Modified By | $Author: u59323933 $ |
| 2014-10-16 (v1.0) | Created (mbgh) |
| keyExpansion | The present design implements the key expansion for the 128-bit version of the Advanced Encryption Standard (AES). |
| Ports | |
| Clk_CI | System clock. |
| Reset_RBI | Asynchronous, active-high reset. |
| Start_SI | Determines whether a new cipherkey has been applied or not. |
| Cipherkey_DI | The cipher key (master key) for the encryption. |
| Roundkeys_DO | The generated round keys. |
| Types | |
| byteArrayType | An array holding 10 bytes. |
| subWordArrayType | An array holding 10 words. |
| expkeyArrayType | An array holding the 44 words, containing all of the roundkeys (including the cipherkey for the first round). |
| rconArrayType | An array holding 10 words (for the round constants). |
| Methods | |
| to_logic | Converts four Words into a logic [127:0]. |
| xor_words | An exclusive-or (XOR) operation for two Words. |
Converts four Words into a logic [127:0].
function logic [127:0] to_logic
An exclusive-or (XOR) operation for two Words.
function Word xor_words